1. Field of the Invention
The present invention relates to a phase-lock loops, and particularly to a phase-lock loop for preventing frequency drift and jitter.
2. Description of Related Art
With the improvement of electronic technology, a variety of applications can be provided by electronic products. For example, local area networks serve to provide a network connection function to a personal computer. In a currently used Ethernet communication protocol, 125 MHz is used as an operating frequency of the transmitter and receiver. However, in other applications, especially in TV images, 14.318 MHz is used as an operating frequency. Therefore, as these two applications are commonly used in a single printed circuit board (PCB), it is unavoidable that two oscillators are used to generate 14.318 MHz and 125 MHz.
Since modern demands of the public users that electronic products must be as compact as possible, two oscillators are used in one electronic product will cause the product to be excessively large and the cost is accordingly too high. Thereby, there is an eager demand for generating the two frequencies by a single oscillator. Moreover, the 14.318 MHz oscillator is cheaper than the 125 MHz oscillator. Thereby, one effective method is to use an oscillator of 14.318 MHz on the PCB, while the phase-lock loop is used to oscillate the 14.318 MHz into 125 MHz.
However, 125 MHz is not integral times of 14.318 MHz. Thus, in fact, it is impossible to oscillate 14.318 MHz into 125 MHz directly. Accordingly, in a practical implementation, the frequency of 14.318 MHz is divided by a large quantity (for example several hundreds) first, and then multiply the divided frequency to be near 125 MHz. However, this conventional method has some disadvantages, such as the phase-lock loop for oscillating several hundred times will have a long duration jitter and the acquired frequency is not exactly equal to 125 MHz and then frequency drift will be generated.
A phase-locked loop (PLL) with a fractional phase swallowing circuit is described in U.S. Pat. No. 5,889,436, entitled “Phase Locked Loop Fractional Pulse Swallowing Frequency Synthesizer”. A low jitter fractional divider is described in U.S. Pat. No. 5,910,110, entitled “Precise, Low Jitter Fractional Divider Using Counter of Rotating Clock Phases”. Although a state machine coupled to a divider is described in FIG. 3 and FIG. 7 of U.S. Pat. No. 5,889,436, but this application presents that “the frequency synthesizer generates a synthesized output signal with low jitter” and “Divider may be deleted, depending upon the desired output frequency”.
Therefore, there is a need to have a novel design for a phase-locked loop that can mitigate and/or obviate the aforementioned problems.